1. Field of the Invention
The present invention relates to a reference current source circuit capable of outputting a constant current even if surrounding environments such as temperature and power source voltage change.
2. Description of the Related Art
Following rapid development of network environment, downscaling of information and communication devices and the like, we can expect realization of ubiquitous networking society in near future. In the ubiquitous networking society, we can obtain various pieces of necessary information from sensor devices buried in whatever locations around us. In order to realize such a society, it is essential to develop a smart sensor LSI sensing information surrounding us. Such a smart LSI should operate continuously over a long period of time with ultralow power consumption, so that it is necessary to acquire power from ambient energy or use a micro battery as a power source. In any case, it is necessary to make the smart sensor LSI operate by supply of quite limited power.
The power consumption of CMOS (Complementary Metal Oxide Semiconductor) LSI has been reduced by downscaling of elements and reduction of power source voltage following the downscaling so far. However, it is difficult to considerably reduce power consumption in a current circuit design on the premise that a metal-oxide-semiconductor field effect transistor (referred to as “MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)”, hereinafter) operates in a strong inversion region. In the present specification and the like, a p channel MOSFET is referred to as “pMOSFET” or “pMOS”, and an n channel MOSFET is referred to as “nMOSFET” or “nMOS”.
Therefore, as a method of considerably reducing power consumption of such a circuit system, there is proposed making a circuit design on the premise that a MOSFET operates in a sub-threshold region. Since current when the MOSFET operates in the sub-threshold region is in an order of nanoamperes (nA), the power consumption of the circuit system can be held down to be equal to or smaller than power in an order of microwatts (μW). On assumption that a circuit is made to operate with a microenergy source such as a button battery, it is possible to construct a circuit system capable of continuously operating over a few years.
Prior art documents relating to the present invention are as follows.
Patent Document 1: Japanese Patent Laid-Open Publication No. JP 11-231955 A;
Patent Document 2: Japanese Patent Laid-Open Publication No. JP 2001-344028 A;
Patent Document 3: Japanese Patent Laid-Open Publication No. JP 2005-301410 A;
Non-Patent Document 1: R. Jacob Baker et al., “CMOS CIRCUIT DESIGN, LAYOUT, AND SIMULATION”, IEEE Press Series on Microelectronic Systems, 2004.
Non-Patent Document 2: H. J. Oguey et al., “CMOS Current Reference Without Resistance”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1132-1135, July 1997;
Non-Patent Document 3: T. Hirose et al., “Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs”, IEICE Electronics Express, Vol. 5, No. 6, pp. 204-210, June 2008;
Non-Patent Document 4: K. Ueno et al., “A 0.3-μW, 7 ppm/° C. CMOS voltage reference circuit for on-chip process monitoring in analog circuits”, Proceedings of the 34th European Solid-State Circuits Conference, pp. 398-401, September 2008;
Non-Patent Document 5: Kenichi Ueno et al., “Reference Voltage Source Circuit for Technique of Correcting Variation of Inter-chip Characteristics in CMOS Analog Circuit”, VDEC Designer Forum 2008, P-09, June 2008;
Non-Patent Document 6: Kazuma Yoshii et al., “Current Reference for Subthreshold LSIs”, Journal of General Conference of the Institute of Electronics, Information and Communication Engineers (IEICE), Electronics, C-12-29, issued by IEICE, March 2007; and
Non-Patent Document 7: K. Ueno et al., “Current reference circuit for subthreshold CMOS LSIs”, 2008 International Conference on Solid State Devices and Materials, Tukuba, Japan, pp. 1000-1001, September 2008.
Although the circuit design on the premise that the MOSFET operates in the sub-threshold region can reduce power consumption, the characteristics of the MOSFET in such an operation region change sensitively to temperature change and process variations. Since the smart sensor LSI is predicted to be used in various environments, it is impossible to ignore such characteristic changes. In order to make such a circuit system operate stably, it is necessary to always supply constant current to the circuit system in every environment. First of all, to this end, it is necessary to construct a reference source circuit that stably operates despite changes in temperature and power source voltage.
The reference source circuit according to prior art will be first described. The carrier mobility and voltage-to-current characteristics of the MOSFET as well as a current mirror circuit that plays an important role in the current source circuit will be described below. In addition, operation principal of an existing reference current source circuit will be described.
The carrier mobility of the MOSFET will first be described. The MOSFET is a unipolar device that operates according to a kind of carriers (electrons for nMOS and holes for pMOS). The carriers in silicon move by drift that occurs in the presence of an electric field and diffusion that occurs due to a concentration gradient of electrons or holes. The drift current will be addressed herein. When an electric field is applied to a medium having free carriers and conductivity, the carriers are accelerated and obtain drift velocity superimposed on a thermal random motion. In a low electric field, a drift velocity Vd is proportional to field intensity ε. A proportional coefficient is referred to as “mobility” and the drift velocity Vd and the field intensity ε hold the following relationship as represented by Equation (1):vd=με  (1),
where mobility μ is inversely proportional to an effective mass of the carriers. Since electrons are smaller in mass than holes, the mobility of the electrons is larger than that of the holes. A carrier scattering mechanism includes phonon scattering (thermal oscillation), impurity scattering, inter-carrier clone scattering, and scattering by neutral impurity atoms. At high temperature, the phonon scattering dominantly occurs and the mobility μ (T) is represented by the following Equation (2):
                              μ          ⁡                      (            T            )                          =                              μ            ⁡                          (                              T                0                            )                                ⁢                                                    (                                  T                                      T                    0                                                  )                                            -                m                                      .                                              (        2        )            
That is, the mobility μ(T) has properties of becoming smaller as temperature T is higher. In this case, To denotes room temperature and m denotes a temperature coefficient of the mobility dependent on CMOS technology. The electron mobility differs from the hole mobility in a value of the temperature coefficient m. Accordingly, an nMOS using electrons as carries differs from a pMOS using holes as carriers in the temperature dependence.
FIG. 1 is a graph showing characteristics of a gate-source voltage VGS to a drain current (on linear scale) ID of a MOSFET according to prior art. FIG. 2 is a graph showing characteristics of the gate-source voltage VGS to a drain current (on logarithmic scale) ID of the MOSFET according to prior art. Referring to FIGS. 1 and 2, a region where the gate-source voltage VGS is higher than a threshold voltage VTH is referred to as “strong inversion region”, and a region where the gate-source voltage VGS is lower than the threshold voltage VTH is referred to as “sub-threshold inversion region” (weak inversion region). Referring to FIG. 1, the drain current ID appears to increase so as to depend on a voltage (VGS−VTH) in the strong inversion region. However, as apparent from FIG. 2, if the drain current ID is represented by a value on logarithmic scale, the current in the sub-threshold region is not zero but a minute current flows in the same region.
FIG. 3 is a graph showing characteristics of a drain-source voltage VDS to the drain current ID of the MOSFET according to prior art. That is, FIG. 3 shows relationship between the drain-source voltage VDS and the drain current ID in the strong inversion region. In FIG. 3, a left side (VDS<VGS−VTH) of a dotted line is referred to as “linear characteristic region (non-saturation characteristic region)”, and a right side (VDS>VGS−VTH) of the dotted line is referred to as “saturation characteristic region”. In the linear characteristic region, the drain current ID depends on the drain-source voltage VDS and is represented by the following Equation (3):
                                          I            D                    =                                    β              ⁡                              [                                                      (                                                                  V                        GS                                            -                                              V                        TH                                                              )                                    -                                                            1                      2                                        ⁢                                          V                      DS                                                                      ]                                      ⁢                          V              DS                                      ,                            (        3        )            
where β=μCOXK, μ denotes the carrier mobility, COX denotes a capacity of an oxide film per unit area, K denotes an aspect ratio (=W/L), W denotes a gate width, and L denotes a gate length. When the drain-source voltage VDS is sufficiently low, the Equation (3) can be approximated to the following Equation (4):ID=β(VGS−VTH)VDS   (4).
According to the Equation (4), the MOSFET operating in this region can be dealt with as a large resistance when the VDS is low enough. In the saturation region, the Equation (3) can be approximated to the following Equation (5):
                              I          D                =                              β            2                    ⁢                                                    (                                                      V                    GS                                    -                                      V                    TH                                                  )                            2                        .                                              (        5        )            
Since the drain current ID can be represented by the Equation (5), the drain current ID is decided by the gate-source voltage VGS without depending on the drain-source voltage VDS.
As mentioned above, the minute current flows in the MOSFET in the sub-threshold region. Due to this, by adopting the circuit design on the premise of this region, power consumption of the circuit system can be considerably reduced. The drain current ID of the MOSFET in this case is represented by the following Equation (6) when the drain-source voltage VDS is, for example, equal to or lower than 0.1 V (in sub-threshold linear region):
                                          I            D                    =                                    KI              0                        ⁢                                          exp                ⁡                                  (                                                                                    V                        GS                                            -                                              V                        TH                                                                                    η                      ⁢                                                                                          ⁢                                              V                        T                                                                              )                                            ⁡                              [                                  1                  -                                      exp                    ⁡                                          (                                              -                                                                              V                            DS                                                                                V                            T                                                                                              )                                                                      ]                                                    ,                            (        6        )            
where IO=μCOXVT2(η−1), VT(=kT/q) denotes a thermal voltage, k denotes Boltzmann coefficient, T denotes an absolute temperature, q denotes a charge elementary quantity, and η denotes a sub-threshold swing coefficient. Furthermore, the drain current ID can be approximated to the following Equation (7) if the drain-source voltage VDS is, for example, equal to or higher than 0.1 V:
                              I          D                =                              KI            0                    ⁢                                    exp              ⁡                              (                                                                            V                      GS                                        -                                          V                      TH                                                                            η                    ⁢                                                                                  ⁢                                          V                      T                                                                      )                                      .                                              (        7        )            
Since the drain current ID can be approximated to the Equation (7), the drain current ID is decided by the gate-source voltage VGS without depending on the drain-source voltage VDS.
FIG. 4 is a circuit diagram showing a current mirror circuit according to prior art. As mentioned above, in the saturation characteristic region, the drain current ID is decided by the gate-source voltage VGS without depending on the drain-source voltage VDS. If two MOSFET M1 and MOSFET M2 operating in such a characteristic region are connected as shown in FIG. 4, the MOSFETs M1 and M2 are the same in the gate-source voltage VGS. Therefore, based on the Equation (5), an output current Iout is represented by the following Equation (8):
                              I          out                =                                            K              2                                      K              1                                ⁢                                    I              ref                        .                                              (        8        )            
Accordingly, various currents can be obtained according to aspect ratios K1 and K2 of the MOSFETs Ml and M2, respectively. As long as the MOSFETs M1 and M2 are equal in size to each other, the same current can be copied for the MOSFETs Ml and M2 without depending on drain voltages. The same thing is true for an instance in which the drain-source voltage VDS is, for example, equal to or higher than 0.1 V in the sub-threshold region. However, the drain current ID of an actual MOSFET depends on the drain-source voltage VDS due to a channel length modulation effect. If the MOSFET is in the strong inversion region, the drain current ID is represented by the following Equation (9):
                              I          D                =                              β            2                    ⁢                                    (                                                V                  GS                                -                                  V                  TH                                            )                        2                    ⁢                                    (                              1                +                                  λ                  ⁢                                                                          ⁢                                      V                    DS                                                              )                        .                                              (        9        )            
Therefore, a difference in the drain-source voltage VDS between the MOSFETs M1 and M2 generates a slight error between a reference output current Iref and the output current Iout. In this case, λ denotes a channel length modulation coefficient that is proportional to 1/L. Thus, the error becomes smaller as the gate length L is larger.
In the current mirror circuit shown in FIG. 4, if the output voltage changes by ΔVout, the output current changes via an output resistance ro2 of the MOSFET M2. If this change in the current is assumed as ΔIout, the ΔIout is represented by the following Equation (10):
                              Δ          ⁢                                          ⁢                      I            out                          =                                            Δ              ⁢                                                          ⁢                              V                out                                                    r                              o                ⁢                                                                  ⁢                2                                              .                                    (        10        )            
Accordingly, as the output resistance ro2 is larger, the change ΔIout in the output current becomes smaller and accuracy of the current mirror circuit improves.
FIG. 5 is a circuit diagram showing a cascode current mirror circuit according to prior art. Examples of a method of increasing the output current include cascode connection shown in FIG. 5. By the cascode connection, the drain resistance ro2 of the MOSFET M2 is changed to (gm4ro4)ro2 that is a multiple of MOSFET M4 by a genuine gain gm4ro4. Accordingly, the change ΔIout in the output current is represented by the following Equation (11):
                              Δ          ⁢                                          ⁢                      I            out                          =                                            Δ              ⁢                                                          ⁢                              V                out                                                                    (                                                      g                                          m                      ⁢                                                                                          ⁢                      4                                                        ⁢                                      r                                          o                      ⁢                                                                                          ⁢                      4                                                                      )                            ⁢                              r                                  o                  ⁢                                                                          ⁢                  2                                                              .                                    (        11        )            
According to the Equation (10), the change ΔIout in the output current can be further suppressed by as much as a genuine gain gm4ro4 of the MOSFET M4. However, if the cascode connection is used, a pair of MOSFETs is additionally connected. Due to this, it is necessary to consume extra voltage (overdrive voltage) required for the MOSFETs to operate, disadvantageously with increasing a lower limit value of the power source voltage.
FIG. 6 is a circuit diagram showing a feedback operational amplifier according to prior art. Referring to FIG. 6, a voltage of an output terminal of an operational amplifier 53 changes so as to eliminate a difference between input signals by function of a feedback circuit 54 if the feedback circuit 54 negatively feeds back a part of the output signal to the operational amplifier 53. In this way, voltages of two input terminals of the feedback target operational amplifier 53 are made be equal to each other, and this state is referred to as “virtual short-circuit”. As mentioned above, the accuracy of the current mirror circuit is improved as the difference in the drain-source voltage VDS between the two MOSFETs is smaller. Accordingly, if the virtual short-circuit of the operational amplifier 53 is used, then the two MOSFETs coincide with each other in VDS, and the accuracy of the current mirror circuit can be improved.
FIG. 7 is a circuit diagram showing a beta-multiplication self-referencing bias circuit according to prior art (See, for example, the Non-Patent Document 1). MOSFETs Mp1 and Mp2 have a common gate-source voltage, and configure one current mirror circuit. Thus, the same current flows in the two MOSFETs Mp1 and Mp2. Accordingly, the same current flows in MOSFETs Mn1 and Mn2. If these MOS transistors are made to operate in the sub-threshold region, both currents therefor can be represented by the Equation (7). However, since a resistance R is connected to a source of the MOSFET Mn1, a gate-source voltage VGSn1 of the MOSFET Mn1 is lower than a gate-source voltage VGSn2 of the MOSFET Mn2. Therefore, it is necessary to adjust the MOSFETs Mn1 and Mn2 to satisfy the following Equation (12):VR+VGSn1=VGSn2   (12),
where VR denotes a voltage as applied to the resistance R. As apparent from a circuit configuration of FIG. 7, the same current flows in this entire circuit, and the current thus flowing is decided by a magnitude of the resistance R. However, it is disadvantageously necessary to set the current flowing in the circuit in an order of several nanoamperes (nA) so as to make the beta-multiplication self-referencing bias circuit operate in the sub-threshold region. Thus, it is necessary to make the resistance R a significantly large resistance, as a result, a chip area disadvantageously increases.
FIG. 8 is a circuit diagram showing a configuration of a reference current source circuit according to a first prior art disclosed in the Non-Patent Document 2. In this circuit, a MOSFET MR is made to operate in a strong inversion linear region and a MOSFET MB is made to operate in a strong inversion saturation region so as to apply a sufficiently high bias voltage to the MOSFET MR. As mentioned above, the MOS transistor operating in the strong inversion region can be dealt with as the resistance, it is possible to prevent an increase in a chip area caused by the resistance, which is a problem with a beta-multiplication self-referencing bias circuit. The operation principle of this circuit will be described below.
A current generated in the circuit is decided by the MOSFET MR (current generation transistor), which operates in the strong inversion linear region. That is, a current I flowing in the circuit is represented by the following Equation (13) based on the Equation (4):I=βR(VB−VTH)VDSR   (13),
where βR denotes a design parameter of the MOSFET MR, VB denotes a bias voltage applied to a gate of the MOSFET MR, and VDSR denotes a drain-source voltage of the MOSFET MR. Since MOSFETs Mn1 and Mn2 shown in FIG. 8 operate in the sub-threshold region, a drain-source voltage VDSR is represented by the following Equation (14) based on the Equation (4):VDSR=ηVT ln(K1/K2)   (4).
Based on this, a minute current can be generated by controlling the design parameter βR and the drain-source voltage VDSR of the MOSFET MR. The temperature dependence of the current represented by the Equations (13) and (14) is considered. The temperature dependences of a carrier mobility μ and a threshold voltage VTH are represented by the following Equations (15) and (16), respectively:
                              μ          =                                    μ              ⁡                              (                                  T                  0                                )                                      ⁢                                          (                                  T                                      T                    0                                                  )                                            -                m                                                    ,        and                            (        15        )                                                      V            TH                    =                                    V                              TH                ⁢                                                                  ⁢                0                                      -                          κ              ⁢                                                          ⁢              T                                      ,                            (        16        )            
where μ(T0) denotes a mobility at room temperature, m denotes a temperature coefficient of the mobility dependent on CMOS technology, VTH0 denotes a threshold voltage at absolute zero point, κ denotes a temperature coefficient of the threshold voltage. In this case, a temperature coefficient TCI of an output current I is represented by the following Equation (17):
                                                                        TC                I                            =                            ⁢                                                                    1                    I                                    ⁢                                                            ⅆ                      I                                                              ⅆ                      T                                                                      =                                                                            1                                              β                        R                                                              ⁢                                                                  ⅆ                                                  β                          R                                                                                            ⅆ                        T                                                                              +                                                            1                                                                        V                          B                                                -                                                  V                          TH                                                                                      ⁢                                                                  ⅆ                                                  (                                                                                    V                              B                                                        -                                                          V                              TH                                                                                )                                                                                            ⅆ                        T                                                                              +                                                                                                                      ⁢                                                1                                      V                    DSR                                                  ⁢                                                      ⅆ                                          V                      DSR                                                                            ⅆ                    T                                                                                                                          =                            ⁢                                                                    1                    -                    m                                    T                                +                                                      1                                                                  V                        B                                            -                                              V                        TH                                                                              ⁢                                                            ⅆ                                              (                                                                              V                            B                                                    -                                                      V                            TH                                                                          )                                                                                    ⅆ                      T                                                                                                                              (        17        )            
Moreover, since the MOSFET MB shown in FIG. 8 operates in the saturation region, a bias voltage VB as applied to a gate of the MOSFET MB is represented by the following Equation (18):
                              V          B                =                              V            TH                    +                                                                      2                  ⁢                                                                          ⁢                  I                                                  β                  B                                                      .                                              (        18        )            
Accordingly, the Equation (17) is represented by the following Equation (19):
                              TC          I                =                                            2              -              m                        T                    .                                    (        19        )            
Since a value of a parameter m of an ordinary MOSFET is about 1.5, the temperature coefficient of the output current is always positive. That is, the ordinary MOSFET has such characteristics that the current increases according to rise in temperature. Based on this, this current source circuit is referred to as “PTC (Positive Temperature Coefficient) current source circuit”, hereinafter. If the PTC current source circuit is used in an environment in which operating temperature changes, the output current from this current source circuit increases according to temperature and such a problem that the current source circuit cannot supply constant current occurs.
FIG. 9 is a circuit diagram showing a configuration of a reference voltage source circuit according to a second prior art disclosed in the Non-Patent Documents 4 and 5. It is reported that this circuit is used as a voltage source and it is not assumed that this circuit is used as a current source. However, a current of the circuit has characteristic property. That is, the circuit has characteristics of being capable of stably generating a current despite variations in a threshold voltage. Referring to FIG. 9, the circuit is configured to include a current source sub-circuit 51 and a voltage source sub-circuit 52. The sizes of respective MOS transistors are set so that a temperature coefficient of an output voltage Vref generated by the voltage source sub-circuit 52 is zero, and this leads to that the output voltage Vref is represented by the following Equation (20):Vref=VTH0   (20).
Since a current generation transistor MR is biased by this output voltage Vref, the output current I from this circuit is represented by the following Equation (21) based on the Equations (7), (13), and (16):I=βRκTVDSR   (21),VDSR=ηVT ln(K1/K2)   (22).
A temperature coefficient TCI of the output circuit I of this circuit is represented by the following Equation (23) based on the Equation (17):
                              TC          I                =                                            1              I                        ⁢                                          ⅆ                I                                            ⅆ                T                                              =                                                    2                -                m                            T                        .                                              (        23        )            
Accordingly, the temperature coefficient TCI of the output current I from the circuit is always positive. That is, the current increases according to rise in temperature. In the reference current source circuit according to the first prior art, the gate-source voltage VGS of the MOSFET MR is biased which operates in the strong inversion saturation region as represented by the Equation (18). The output current is represented by the following Equation (24):
                    I        =                              β            R                    ⁢                                                    2                ⁢                                                                  ⁢                I                                            β                B                                              ⁢                                    V              DSR                        .                                              (        24        )            
On the other hand, in this circuit, a threshold voltage of each MOSFET is biased to absolute zero point. The output current I is represented by the Equation (21). In the Equation (24), a value of
            2      ⁢                          ⁢      I              β      B      changes according to variations in manufacturing process. On the other hand, κT in the Equation (21) is stable despite the process variations. Therefore, it can be predicted that the output current from this circuit has less influence on the process variations.
FIG. 10 is a circuit diagram showing a configuration of a reference current source circuit according to a third prior art disclosed in, for example, the Non-Patent Document 6. The reference current source circuits according to the first and second prior arts have such a problem that the current increases in proportion to the temperature. In order to solve this problem, the Non-Patent Document 6 discloses the following respects. A current source circuit having such characteristics that the current decreases in proportion to the temperature, that is, an NTC (Negative Temperature Coefficient) current source circuit is separately provided, and the currents of these circuits are added up, and this leads to improvement in the temperature characteristics of the current.
The circuit of FIG. 10 is configured to include a PTC current source circuit 61, an NTC current source circuit 62, and a current adder circuit 63. The circuit adopts cascode connection to improve the current mirror circuit. The NTC current source circuit 62 is configured so that a MOSFET MB2 operating in the sub-threshold region and a MOSFET MB3 operating in the saturation region are connected to each other in place of a MOSFET MB1 of the PTC current source circuit 61. In this case, a gate-source voltage VB2 of a current generation transistor MR2 of the NTC current source circuit 62 is represented by the following Equation (25):
                              V                      B            ⁢                                                  ⁢            2                          =                              2            ⁢                                                  ⁢                          V              TH                                +                                                    2                ⁢                                                                  ⁢                I                                            β                                  B                  ⁢                                                                          ⁢                  3                                                              +                      η            ⁢                                                  ⁢                          V              T                        ⁢                                          ln                ⁡                                  (                                      I                                                                  K                                                  B                          ⁢                                                                                                          ⁢                          2                                                                    ⁢                                              I                        0                                                                              )                                            .                                                          (        25        )            
A temperature coefficient TCI of an output current Iref is represented by the following Equation (26) based on the Equations (17) and (25):
                                          TC            I                    =                                                    2                -                m                            T                        -                          1                              T                ⁡                                  (                                      1                    -                                                                                            κ                          ⁢                                                                                                          ⁢                          T                                                -                                                  V                          A                                                                                            V                                                  TH                          ⁢                                                                                                          ⁢                          0                                                                                                      )                                                                    ,                            (        26        )            
where T denotes the temperature, VTH0 denotes a threshold voltage at the absolute zero point, κ denotes a temperature coefficient of the threshold voltage, and the voltage VA is represented by the following Equation (27):
                              V          A                =                                            1              2                        ⁢                                                            2                  ⁢                                                                          ⁢                  I                                                  β                                      B                    ⁢                                                                                  ⁢                    3                                                                                +                      η            ⁢                                                  ⁢                          V              T                        ⁢                          ln              ⁡                              (                                  I                                                            K                                              B                        ⁢                                                                                                  ⁢                        2                                                              ⁢                                          I                      0                                                                      )                                              -                      η            ⁢                                                  ⁢                                          V                T                            .                                                          (        27        )            
In this case, since a parameter κT is a very small value as compared with the threshold voltage VTH0 at the absolute zero point, the Equation (26) is represented by the following Equation (28):
                              TC          I                =                                                            2                -                m                            T                        -                                          1                T                            ⁢                              (                                  1                  +                                                            κ                      ⁢                                                                                          ⁢                      T                                                              V                                              TH                        ⁢                                                                                                  ⁢                        0                                                                                            )                                              =                                                    1                -                m                            T                        -                                          κ                                  V                                      TH                    ⁢                                                                                  ⁢                    0                                                              .                                                          (        28        )            
Accordingly, the temperature coefficient TCI of the output current I from the NTC current source circuit 62 is always negative. Based on the aforementioned, the current generated by the PTC current source circuit 61 and having the positive temperature coefficient and the current generated by the NTC current source circuit 62 and having the negative temperature coefficient are inputted to the current adder circuit 63. It is thereby possible to configure the reference current source circuit (FIG. 10) that outputs a current the temperature coefficient of which is zero. It is noted that the voltage VB2 represented by the Equation (25) is applied as a bias voltage to the current generation transistor MR2 of the NTC current source circuit 62. Therefore, an output current INTC from the NTC current source circuit 62 is represented by the following Equation (29) based on the Equations (13) and (25):
                              I          NTC                =                                            β                              R                ⁢                                                                  ⁢                2                                      ⁡                          (                                                V                  TH                                +                                                                            2                      ⁢                                              I                        NTC                                                                                    β                                              B                        ⁢                                                                                                  ⁢                        3                                                                                            +                                  η                  ⁢                                                                          ⁢                                      V                    T                                    ⁢                                      ln                    ⁡                                          (                                                                        I                          NTC                                                                                                      K                                                          B                              ⁢                                                                                                                          ⁢                              2                                                                                ⁢                                                      I                            0                                                                                              )                                                                                  )                                ⁢                                    V              DS                        .                                              (        29        )            
Now, attention is paid to the Equations (28) and (29). Each of the both Equations (28) and (29) includes the threshold voltage VTH (∞VTH0). The threshold voltage VTH0 at the absolute zero point greatly changes with respect to process variations and current characteristics greatly change. Accordingly, with the technique of generating the constant current using such an NTC current source circuit 62, the current characteristics are possibly changed by the process variations. The problems of the prior art mentioned so far will be put into shape as follows.
A technique of generating a constant current using a voltage source circuit referring to a band-gap of silicon has been conventionally adopted (See, for example, the Patent Document 1). FIG. 11A is a chart showing a method of generating a constant current according to the prior art, that is, a graph showing temperature changes of a PTAT (Proportional To Absolute Temperature) current 71 that increases in proportion to the temperature and a CTAT (Conversely Proportional To Absolute Temperature) current 72 that decreases in proportion to the temperature. FIG. 11B is a graph showing that the constant current is obtained by adding up the PTAT current 71 and the CTAT current 72 shown in FIG. 11A. That is, as shown in FIGS. 11A and 11B, it is possible to obtain the current that is constant despite temperature change by adding the PTAT current 71 and the CTAT current 72.
However, the band-gap voltage source circuit has a problem of high electric power and such a problem that a package area increases when the band-gap voltage source circuit is made to operate with low current because of use of a resistance. These current source circuits generate the current increasing and the current decreasing according to the temperature as circuits, respectively, and generate the constant current that does not change with respect to temperature by adding up these currents.
The above-mentioned first and second prior arts propose the power source circuits operating in the minute current region in an order of nanoamperes. The current flowing in each of these circuits has characteristics of increasing in proportion to the temperature. According to the third prior art, the reference current source circuit has such characteristics that a constant current can be obtained even with a temperature change but that the current is strongly influenced by variations of a threshold voltage, and that the current has great change. According to the first and second prior arts, the reference current source circuits operate stably against process variations but have the following problems. FIG. 12A is a graph showing that a minute current generator circuit according to the prior art cannot generate the CTAT current 72. FIG. 12B is a graph showing that the minute current generator circuit according to the prior art cannot obtain a reference current output without temperature dependence as a result of FIG. 12A. As shown in FIGS. 12A and 12B, the reference voltage source circuit referring to the band-gap according to the prior art cannot generate the current decreasing according to temperature, and a reference current source circuit generating a current constant with respect to temperature cannot be constructed.